The problem of crack formation in thin sublayers of silicon oxide during pulsed heating of interconnects

Abstract

It is well known that in modern micro- and nanoelectronics thin-film structures are actively used as a gate dielectric, passivating layers, membranes, etc. The research is devoted to the problem of crack formation in thin sublayers of silicon oxide during pulsed heating of interconnects on single-crystal silicon wafers. The purpose of the paper is to study the effect of surface sources of thermal shock on the cracks formation in films and aspects of crack formation in SO2 films have been studied in detail. Experimental verification of the estimates made was carried out on multilayer structures of a silicon substrate-silicon oxide sublayer-aluminum film (Si-SiO₂-Al). As substrates, it was used phosphorus-doped silicon single-crystal wafers oriented in the (111) direction, with a resistivity in the range p = 0.1 ?.?m. The authors studied the temperature fields in silicon wafers (Al-Si system) and silicon oxide wafers (Al-SiO2 system) heated by a surface metallization layer both for the case of a point heat source and for the case of a long rectangular metallization path (provided that the track length significantly exceeds its width). The calculation results showed that the temperature profile of the metallization path (width 75 ?m) in the transverse direction is heterogeneous. It was also shown that, in contrast to SiO2 films, the level of appearing mechanical stresses in silicon is insufficient for the formation of cracks near the source of thermal shock. This is due to a higher tensile strength than that of oxide.