Characterization and synthesis of a 32-bit asynchronous microprocessorin synchronous reconfigurable devices

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Adrián Pedroza de la Crúz
José Roberto Reyes Barón
Susana Ortega Cisneros
Juan José Raygoza Panduro
Miguel Ángel Carrazco Díaz
José Raúl Loo Yau

Abstract

2015AbstractThis paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronousreconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction,and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of themicroprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of theasynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralizedgenerator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This workcompares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Bothcircuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against1.6 MIPS for the synchronous.All Rights Reserved © 2015 Universidad Nacional Autónoma de México, Centro de Ciencias Aplicadas y Desarrollo Tecnológico. This is anopen access item distributed under the Creative Commons CC License BY-NC-ND 4.0.

 

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Pedroza de la Crúz, A., Reyes Barón, J. R., Ortega Cisneros, S., Raygoza Panduro, J. J., Carrazco Díaz, M. Ángel, & Loo Yau, J. R. (2015). Characterization and synthesis of a 32-bit asynchronous microprocessorin synchronous reconfigurable devices. Journal of Applied Research and Technology, 13(5). https://doi.org/10.1016/j.jart.2015.10.004