Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to- Digital Converter Based on a Polyphase Demultiplexing Architecture

Abstract

In this paper we present the practical implementation of a high-speed polyphase sampling and demultiplexingarchitecture for optoelectronics analog-to-digital converters (OADCs). The architecture consists of a one-stage divideby-eight decimator circuit where optically-triggered samplers are cascaded to sample an analog input signal, anddemultiplex different phases of the sampled signal to yield low data rate for electronic quantization. Electrical-in toelectrical-out data format is maintained through the sampling, demultiplexing and quantization processes of thearchitecture thereby avoiding the need for electrical-to-optical and optical-to-electrical signal conversions. Weexperimentally demonstrate a 10.24 giga samples per second (GS/s), 12-bit resolution OADC system comprising theoptically-triggered sampling circuits integrated with commercial electronic quantizers. Measurements performed on theOADC yielded an effective bit resolution (ENOB) of 10.3 bits, spurious free dynamic range (SFDR) of -32 dB andsignal-to-noise and distortion ratio (SNDR) of 63.7 dB.